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» Partitioning of VLSI Circuits and Systems
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ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
15 years 6 months ago
Integrated circuit design with NEM relays
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...
Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King L...
DAC
2007
ACM
15 years 10 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
71
Voted
CODES
2008
IEEE
15 years 4 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
15 years 3 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
84
Voted
GLVLSI
2003
IEEE
175views VLSI» more  GLVLSI 2003»
15 years 3 months ago
A custom FPGA for the simulation of gene regulatory networks
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
Ilias Tagkopoulos, Charles A. Zukowski, German Cav...