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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
16 years 1 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
ISQED
2010
IEEE
114views Hardware» more  ISQED 2010»
15 years 11 months ago
Toward effective utilization of timing exceptions in design optimization
— Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-function...
Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang
SI3D
2010
ACM
15 years 11 months ago
Interactive volume caustics in single-scattering media
Volume caustics are intricate illumination patterns formed by light first interacting with a specular surface and subsequently being scattered inside a participating medium. Alth...
Wei Hu, Zhao Dong, Ivo Ihrke, Thorsten Grosch, Guo...
159
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MSWIM
2009
ACM
15 years 11 months ago
On providing location privacy for mobile sinks in wireless sensor networks
Wireless sensor networks have attracted increasing attentions considering their potentials for being widely adopted in both emerging civil and military applications. A common prac...
Edith C.-H. Ngai, Ioana Rodhe
SASO
2009
IEEE
15 years 11 months ago
Self-organized Fault-tolerant Routing in Peer-to-Peer Overlays
—In sufficiently large heterogeneous overlays message loss and delays are likely to occur. This has a significant impact on overlay routing, especially on longer paths. The exi...
Wojciech Galuba, Karl Aberer, Zoran Despotovic, Wo...