35 search results - page 3 / 7 » Pattern generation for a deterministic BIST scheme |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
VTS
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
DAC
2003
ACM
13 years 11 months ago
2003
ACM
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
ET
2002
13 years 6 months ago
2002
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...