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ISCAPDCS
2001
15 years 4 months ago
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
129
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AICOM
2010
127views more  AICOM 2010»
15 years 3 months ago
Interactive verification of concurrent systems using symbolic execution
This paper presents an interactive proof method for the verification of temporal properties of concurrent systems based on symbolic execution. Symbolic execution is a well known a...
Simon Bäumler, Michael Balser, Florian Nafz, ...
ACTA
2004
86views more  ACTA 2004»
15 years 3 months ago
Specification transformers: a predicate transformer approach to composition
Abstract. This paper explores theories that help in (i) proving that a system composed from components satisfies a system specification given only specifications of components and ...
Michel Charpentier, K. Mani Chandy
120
Voted
JUCS
2000
120views more  JUCS 2000»
15 years 3 months ago
Compiler Generated Multithreading to Alleviate Memory Latency
: Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing ...
Kristof Beyls, Erik H. D'Hollander
135
Voted
ACSD
2010
IEEE
215views Hardware» more  ACSD 2010»
15 years 1 months ago
A Formal Semantics of Clock Refinement in Imperative Synchronous Languages
The synchronous model of computation divides the execution of a program into an infinite sequence of socalled macro steps, which are further divided into finitely many micro steps....
Mike Gemunde, Jens Brandt, Klaus Schneider