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ICPP
2008
IEEE
15 years 11 months ago
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a f...
Sangyeun Cho, Socrates Demetriades, Shayne Evans, ...
IPPS
2007
IEEE
15 years 10 months ago
A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
Richard T. Saunders, Clinton L. Jeffery, Derek T. ...
KES
2005
Springer
15 years 10 months ago
Bayesian Inference Driven Behavior Network Architecture for Avoiding Moving Obstacles
This paper presents a technique for an intelligent robot to adaptively behave in unforeseen and dynamic circumstances. Since the traditional methods utilized the relatively reliabl...
Hyeun-Jeong Min, Sung-Bae Cho
IPPS
1999
IEEE
15 years 8 months ago
Implementing a Non-Strict Functional Programming Language on a Threaded Architecture
Abstract. The combination of a language with ne-grain implicit parallelism and a data ow evaluation scheme is suitable for high-level programming on massively parallel architectur...
Shigeru Kusakabe, Kentaro Inenaga, Makoto Amamiya,...
HPCA
1997
IEEE
15 years 8 months ago
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication. In compiler-synthesized dynamic branch prediction, the compiler g...
David I. August, Daniel A. Connors, John C. Gyllen...