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157
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ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
15 years 7 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
172
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ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
13 years 6 months ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...
133
Voted
CVPR
2006
IEEE
16 years 5 months ago
Shape Topics: A Compact Representation and New Algorithms for 3D Partial Shape Retrieval
This paper develops an efficient new method for 3D partial shape retrieval. First, a Monte Carlo sampling strategy is employed to extract local shape signatures from each 3D model...
Yi Liu, Hongbin Zha, Hong Qin
123
Voted
HPDC
2008
IEEE
15 years 10 months ago
Key-based consistency and availability in structured overlay networks
Structured Overlay Networks provide a promising platform for high performance applications since they are scalable, fault-tolerant and self-managing. Structured overlays provide l...
Tallat M. Shafaat, Thorsten Schütt, Monika Mo...
163
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AAAI
2007
15 years 6 months ago
Hybrid Inference for Sensor Network Localization Using a Mobile Robot
In this paper, we consider a hybrid solution to the sensor network position inference problem, which combines a real-time filtering system with information from a more expensive,...
Dimitri Marinakis, David Meger, Ioannis M. Rekleit...