1058 search results - page 53 / 212 » Performance Analysis of Mapping Strategies for Parallel Simu... |
127
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AINA
2007
IEEE
15 years 9 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
147
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CCGRID
2006
IEEE
15 years 9 months ago
2006
IEEE
As the scale is expanding, node failure becomes a commonplace feature of large-scale cluster systems. As an important part of cluster operating system software, job scheduling tak...
143
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IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Pr...
115
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DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
109
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IPPS
2007
IEEE
15 years 9 months ago
2007
IEEE
This paper presents the optimization and evaluation of parallel I/O for the BIPS3D parallel irregular application, a 3-dimensional simulation of BJT and HBT bipolar devices. The p...