45 search results - page 8 / 9 » Performance Evaluation of Tiling for the Register Level |
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
CVRMED
1997
Springer
13 years 10 months ago
1997
Springer
The majority of the available rigid registration measures are based on a 2-dimensional histogram of corresponding grey-values in the registered images. This paper shows that these ...
SAS
2000
Springer
13 years 9 months ago
2000
Springer
As compilers increasingly rely on optimizations to achieve high performance, the effectiveness of source level debuggers for optimized code continues to falter. Even if values of s...
DAC
2005
ACM
14 years 7 months ago
2005
ACM
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
PDP
2011
IEEE
12 years 10 months ago
2011
IEEE
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...