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» Performance Evaluation of a Parallel Simulation Environment
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GECCO
2005
Springer
189views Optimization» more  GECCO 2005»
15 years 5 months ago
Molecular programming: evolving genetic programs in a test tube
We present a molecular computing algorithm for evolving DNA-encoded genetic programs in a test tube. The use of synthetic DNA molecules combined with biochemical techniques for va...
Byoung-Tak Zhang, Ha-Young Jang
ICS
2004
Tsinghua U.
15 years 5 months ago
Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches
We propose a novel replacement algorithm, called InterReference Gap Distribution Replacement (IGDR), for setassociative secondary caches of processors. IGDR attaches a weight to e...
Masamichi Takagi, Kei Hiraki
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
15 years 5 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
CF
2010
ACM
15 years 4 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
CAL
2008
14 years 11 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny