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RTCSA
1999
IEEE
15 years 5 months ago
Pipeline Timing Analysis Using a Trace-Driven Simulator
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
Jakob Engblom, Andreas Ermedahl
CORR
2007
Springer
128views Education» more  CORR 2007»
15 years 1 months ago
A Mobile Computing Architecture for Numerical Simulation
The domain of numerical simulation is a place where the parallelization of numerical code is common. The definition of a numerical context means the configuration of resources suc...
Cyril Dumont, Fabrice Mourlin
BC
2004
91views more  BC 2004»
15 years 1 months ago
Simulation and parameter estimation of dynamics of synaptic depression
Abstract. Synaptic release was simulated using a Simulink sequential storage model with three vesicular pools. Modeling was modular and easily extendable to the systems with greate...
F. Aristizabal, M. I. Glavinovic
IPPS
1994
IEEE
15 years 5 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
ISCAPDCS
2007
15 years 2 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi