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2007
Tsinghua U.
15 years 10 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow
ICPADS
2008
IEEE
15 years 10 months ago
Quarc: A Novel Network-On-Chip Architecture
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC [16]. The Quarc scheme significantly outperforms the Spidergon NoC through balancing t...
Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi
IPPS
2006
IEEE
15 years 10 months ago
FPGA based architecture for DNA sequence comparison and database search
DNA sequence comparison is a computationally intensive problem, known widely since the competition for human DNA decryption. Database search for DNA sequence comparison is of grea...
Euripides Sotiriades, Christos Kozanitis, Apostolo...
PPOPP
2006
ACM
15 years 10 months ago
POSH: a TLS compiler that exploits program structure
As multi-core architectures with Thread-Level Speculation (TLS) are becoming better understood, it is important to focus on TLS compilation. TLS compilers are interesting in that,...
Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin ...
IPPS
2005
IEEE
15 years 9 months ago
Packet Routing in Dynamically Changing Networks on Chip
On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication amon...
Mateusz Majer, Christophe Bobda, Ali Ahmadinia, J&...