2964 search results - page 366 / 593 » Performance Prediction of a Parallel Simulator |
139
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ANCS
2006
ACM
15 years 8 months ago
2006
ACM
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
122
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HPCA
2003
IEEE
16 years 4 months ago
2003
IEEE
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications s...
140
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HPCA
2002
IEEE
16 years 4 months ago
2002
IEEE
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
128
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HSNMC
2003
Springer
15 years 9 months ago
2003
Springer
Abstract. Numerous studies have shown that packet reordering is common, especially in high speed networks where there is high degree of parallelism and different link speeds. Reor...
139
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PRESENCE
2010
14 years 11 months ago
2010
This paper focuses on the design of high performance VR applications. These applications usually involve various I/O devices and complex simulations. A parallel architecture or gri...