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DSD
2009
IEEE
144views Hardware» more  DSD 2009»
15 years 4 months ago
Composable Resource Sharing Based on Latency-Rate Servers
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...
Benny Akesson, Andreas Hansson, Kees Goossens
JNW
2007
86views more  JNW 2007»
14 years 9 months ago
Linux Software Router: Data Plane Optimization and Performance Evaluation
- Recent technological advances provide an excellent opportunity to achieve truly effective results in the field of open Internet devices, also known as Open Routers or ORs. Even t...
Raffaele Bolla, Roberto Bruschi
ESA
2006
Springer
140views Algorithms» more  ESA 2006»
15 years 1 months ago
Latency Constrained Aggregation in Sensor Networks
A sensor network consists of sensing devices which may exchange data through wireless communication. A particular feature of sensor networks is that they are highly energy constrai...
Luca Becchetti, Peter Korteweg, Alberto Marchetti-...
ICPADS
2006
IEEE
15 years 3 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
ICPPW
2008
IEEE
15 years 4 months ago
Performance Analysis and Optimization of Parallel Scientific Applications on CMP Cluster Systems
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....
Xingfu Wu, Valerie E. Taylor, Charles W. Lively, S...