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» Performance and Functional Verification of Microprocessors
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JSW
2007
126views more  JSW 2007»
14 years 9 months ago
Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware
— The paper addresses software and firmware implementation of multiple-output Boolean functions based on cascades of Look-Up Tables (LUTs). A LUT cascade is described as a means ...
Vaclav Dvorak
FMCAD
2006
Springer
15 years 1 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
GLOBECOM
2008
IEEE
14 years 9 months ago
On the Impact of Caching for High Performance Packet Classifiers
Hash functions have a space complexity of O(n) and a possible time complexity of O(1). Thus, packet classifiers exploit hashing to achieve packet classification in wire speed. Esp...
Harald Widiger, Andreas Tockhorn, Dirk Timmermann
95
Voted
CSI
2004
186views more  CSI 2004»
14 years 9 months ago
Towards a BioAPI compliant face verification system
Standards are important to the growth and acceptance of emerging industries such as the biometric industry. To promote biometric standard, the BioAPI Consortium has developed a wi...
X. Yuan, Siu Cheung Hui, Maylor K. H. Leung, Yongs...
DAC
1999
ACM
15 years 1 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...