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» Performance and Functional Verification of Microprocessors
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MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
16 years 2 days ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
HPCS
2006
IEEE
15 years 12 months ago
Toward a Software Infrastructure for the Cyclops-64 Cellular Architecture
This paper presents the initial design of the Cyclops-64 (C64) system software infrastructure and tools under development as a joint effort between IBM T.J. Watson Research Center...
Juan del Cuvillo, Weirong Zhu, Ziang Hu, Guang R. ...
ISCAS
2005
IEEE
171views Hardware» more  ISCAS 2005»
15 years 11 months ago
Image transmission over IEEE 802.15.4 and ZigBee networks
An image sensor network platform is developed for testing transmission of images over ZigBee networks that support multi-hopping. The ZigBee is a low rate and low power networking...
G. Pekhteryev, Zafer Sahinoglu, Philip V. Orlik, G...
EMSOFT
2005
Springer
15 years 11 months ago
Compiler-guided register reliability improvement against soft errors
With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely ...
Jun Yan, Wei Zhang
CODES
2005
IEEE
15 years 7 months ago
Hardware/software partitioning of software binaries: a case study of H.264 decode
We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application’s binary are competitive with parti...
Greg Stitt, Frank Vahid, Gordon McGregor, Brian Ei...