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HPDC
2010
IEEE
14 years 10 months ago
A GPU accelerated storage system
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
Abdullah Gharaibeh, Samer Al-Kiswany, Sathish Gopa...
DATE
2003
IEEE
87views Hardware» more  DATE 2003»
15 years 3 months ago
FPGA-Based Implementation of a Serial RSA Processor
In this paper we present an hardware implementation of the RSA algorithm for public-key cryptography. The RSA algorithm consists in the computation of modular exponentials on larg...
Antonino Mazzeo, Luigi Romano, Giacinto Paolo Sagg...
DAC
2004
ACM
15 years 1 months ago
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
ICPR
2002
IEEE
15 years 11 months ago
Graph of Neural Networks for Pattern Recognition
This paper presents a new architecture of neural networks designed for pattern recognition. The concept of induction graphs coupled with a divide-and-conquer strategy defines a Gr...
Hubert Cardot, Olivier Lezoray
PPOPP
2006
ACM
15 years 3 months ago
POSH: a TLS compiler that exploits program structure
As multi-core architectures with Thread-Level Speculation (TLS) are becoming better understood, it is important to focus on TLS compilation. TLS compilers are interesting in that,...
Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin ...