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IPPS
2007
IEEE
15 years 3 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
IPPS
2006
IEEE
15 years 3 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
CCGRID
2010
IEEE
14 years 10 months ago
A High-Level Interpreted MPI Library for Parallel Computing in Volunteer Environments
Idle desktops have been successfully used to run sequential and master-slave task parallel codes on a large scale in the context of volunteer computing. However, execution of messa...
Troy P. LeBlanc, Jaspal Subhlok, Edgar Gabriel
DAC
2004
ACM
15 years 10 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
DAC
2001
ACM
15 years 10 months ago
Speculation Techniques for High Level Synthesis of Control Intensive Designs
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow through conditions and loops in the input description. In...
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dut...