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DAC
2005
ACM
15 years 10 months ago
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
HPDC
2007
IEEE
15 years 4 months ago
An architecture for virtual organization (VO)-based effective peering of content delivery networks
The proprietary nature of existing Content Delivery Networks (CDNs) means they are closed and do not naturally cooperate, resulting in “islands” of CDNs. Finding ways for dist...
Al-Mukaddim Khan Pathan, James Broberg, Kris Buben...
ISPD
2003
ACM
132views Hardware» more  ISPD 2003»
15 years 3 months ago
Architecture and synthesis for multi-cycle communication
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
ICSE
2000
IEEE-ACM
15 years 1 months ago
Software engineering and performance: a road-map
Software engineering has traditionally focussed on functional requirements and how to build software that has few bugs and can be easily maintained. Most design approaches include...
Rob Pooley
DAC
2009
ACM
15 years 10 months ago
PDRAM:a hybrid PRAM and DRAM main memory system
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges in...
Gaurav Dhiman, Raid Ayoub, Tajana Rosing