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DAC
2008
ACM
15 years 11 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
CONCURRENCY
2004
151views more  CONCURRENCY 2004»
14 years 9 months ago
User transparency: a fully sequential programming model for efficient data parallel image processing
Although many image processing applications are ideally suited for parallel implementation, most researchers in imaging do not benefit from high performance computing on a daily b...
Frank J. Seinstra, Dennis Koelma
ATS
2005
IEEE
98views Hardware» more  ATS 2005»
15 years 3 months ago
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
IPPS
2007
IEEE
15 years 4 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
IPPS
2007
IEEE
15 years 4 months ago
A Landmark-based Index Architecture for General Similarity Search in Peer-to-Peer Networks
The indexing of complex data and similarity search plays an important role in many application areas. Traditional centralized index structure can not scale with the rapid prolifer...
Xiaoyu Yang, Yiming Hu