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» Performance evaluation of software architectures
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IOLTS
2006
IEEE
100views Hardware» more  IOLTS 2006»
16 years 9 days ago
A Note on Error Detection in an RSA Architecture by Means of Residue Codes
Recently, various attacks have been proposed against many cryptosystems, exploiting deliberate error injection during the computation process. In this paper, we add a residue-base...
Luca Breveglieri, Paolo Maistri, Israel Koren
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 6 months ago
Rapid Embedded Hardware/Software System Generation
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya,...
HPCA
2008
IEEE
16 years 6 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
ICSE
2007
IEEE-ACM
16 years 12 days ago
Agility and Experimentation: Practical Techniques for Resolving Architectural Tradeoffs
This paper outlines our experiences with making architectural tradeoffs between performance, availability, security, and usability, in light of stringent cost and time-to-market c...
T. C. Nicholas Graham, Rick Kazman, Chris Walmsley
185
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MICRO
2003
IEEE
148views Hardware» more  MICRO 2003»
15 years 11 months ago
Fast Secure Processor for Inhibiting Software Piracy and Tampering
Due to the widespread software piracy and virus attacks, significant efforts have been made to improve security for computer systems. For stand-alone computers, a key observation...
Jun Yang 0002, Youtao Zhang, Lan Gao