176 search results - page 28 / 36 » Performance improvement with circuit-level speculation |
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ISCA
2012
IEEE
12 years 12 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
ASPDAC
2009
ACM
15 years 1 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
Current processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline ...