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» Performance of Switch Blocking on Multithreaded Architecture...
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ICPP
1994
IEEE
15 years 3 months ago
Performance of Switch Blocking on Multithreaded Architectures
K. Gopinath, M. K. Krishna Narasimhan, B. H. Lim, ...
EUC
2008
Springer
15 years 1 months ago
Reducing Context Switch Overhead with Compiler-Assisted Threading
Multithreading is an important software modularization technique. However, it can incur substantial overheads, especially in processors where the amount of architecturally visible...
Pekka Jääskeläinen, Pertti Kellom&a...
112
Voted
ISCAPDCS
2001
15 years 1 months ago
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
ICDCS
1997
IEEE
15 years 3 months ago
Multi-threading and Remote Latency in Software DSMs
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
Kritchalach Thitikamol, Peter J. Keleher
116
Voted
DATE
2007
IEEE
185views Hardware» more  DATE 2007»
15 years 6 months ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha