69 search results - page 6 / 14 » Performance of Switch Blocking on Multithreaded Architecture... |
SIGCOMM
2010
ACM
14 years 9 months ago
2010
ACM
The basic building block of ever larger data centers has shifted from a rack to a modular container with hundreds or even thousands of servers. Delivering scalable bandwidth among...
83
Voted
DSD
2008
IEEE
14 years 11 months ago
2008
IEEE
Caching mechanism has achieved great success in general purpose processor; however, its deployment in Network Processor (NP) raises questions over its effectiveness under the new ...
72
Voted
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
72
Voted
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
Various studies have shown that OS jitter can degrade parallel program performance considerably at large processor counts. Most sources of system jitter fall broadly into 5 catego...
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and...