Sciweavers

69 search results - page 8 / 14
» Performance of Switch Blocking on Multithreaded Architecture...
Sort
View
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Approximation Algorithm for Process Mapping on Network Processor Architectures
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, ...
Christopher Ostler, Karam S. Chatha, Goran Konjevo...
HPCA
2008
IEEE
15 years 10 months ago
Runahead Threads to improve SMT performance
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
Tanausú Ramírez, Alex Pajuelo, Olive...
HPCA
2008
IEEE
15 years 10 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
ISCA
2012
IEEE
208views Hardware» more  ISCA 2012»
13 years 1 days ago
Harmony: Collection and analysis of parallel block vectors
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
Melanie Kambadur, Kui Tang, Martha A. Kim
81
Voted
IPSN
2005
Springer
15 years 3 months ago
eBlocks - an enabling technology for basic sensor based systems
—We describe the development of a set of embedded system building blocks, known as eBlocks. An eBlock network can be viewed as a basic form of sensor network that can be develope...
Susan Cotterell, Ryan Mannion, Frank Vahid, Harry ...