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IPPS
2007
IEEE
15 years 10 months ago
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
Christopher Claus, Florian Helmut Müller, Joh...
CF
2011
ACM
14 years 3 months ago
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazal...
131
Voted
SPAA
1995
ACM
15 years 7 months ago
Provably Efficient Scheduling for Languages with Fine-Grained Parallelism
Many high-level parallel programming languages allow for fine-grained parallelism. As in the popular work-time framework for parallel algorithm design, programs written in such lan...
Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias
119
Voted
PODC
2005
ACM
15 years 9 months ago
Advanced contention management for dynamic software transactional memory
The obstruction-free Dynamic Software Transactional Memory (DSTM) system of Herlihy et al. allows only one transaction at a time to acquire an object for writing. Should a second ...
William N. Scherer III, Michael L. Scott
155
Voted
ECRTS
2009
IEEE
15 years 1 months ago
Precise Worst-Case Execution Time Analysis for Processors with Timing Anomalies
This paper explores timing anomalies in WCET analysis. Timing anomalies add to the complexity of WCET analysis and make it hard to apply divide-and-conquer strategies to simplify ...
Raimund Kirner, Albrecht Kadlec, Peter P. Puschner