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ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 9 months ago
A Scalable Instruction Queue Design Using Dependence Chains
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
Steven E. Raasch, Nathan L. Binkert, Steven K. Rei...
ICS
2003
Tsinghua U.
15 years 9 months ago
Selecting long atomic traces for high coverage
This paper performs a comprehensive investigation of dynamic selection for long atomic traces. It introduces a classification of trace selection methods and discusses existing and...
Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ron...
IPPS
1997
IEEE
15 years 8 months ago
Extensible Message Passing Application Development and Debugging with Python
We describe how we have parallelized Python, an interpreted object oriented scripting language, and used it to build an extensible message-passing molecular dynamics application f...
David M. Beazley, Peter S. Lomdahl
SPAA
2010
ACM
15 years 9 months ago
Towards optimizing energy costs of algorithms for shared memory architectures
Energy consumption by computer systems has emerged as an important concern. However, the energy consumed in executing an algorithm cannot be inferred from its performance alone: i...
Vijay Anand Korthikanti, Gul Agha
CISIS
2011
IEEE
14 years 4 months ago
Improving Scheduling Techniques in Heterogeneous Systems with Dynamic, On-Line Optimisations
—Computational performance increasingly depends on parallelism, and many systems rely on heterogeneous resources such as GPUs and FPGAs to accelerate computationally intensive ap...
Marcin Bogdanski, Peter R. Lewis, Tobias Becker, X...