3321 search results - page 534 / 665 » Performance of parallel computations with dynamic processor ... |
143
Voted
IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
114
Voted
DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
124
Voted
SPAA
2005
ACM
15 years 9 months ago
2005
ACM
One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It ha...
133
Voted
IPPS
2000
IEEE
15 years 8 months ago
2000
IEEE
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
123
Voted
IEEEPACT
1998
IEEE
15 years 7 months ago
1998
IEEE
The fast evolution of processor performance necessitates a permanent evolution of all the multiprocessor components, even for small to medium-scale symmetric multiprocessors (SMP)...