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IPPS
1998
IEEE
15 years 7 months ago
Evaluation of a Low-Power Reconfigurable DSP Architecture
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marl...
SIGMETRICS
1996
ACM
118views Hardware» more  SIGMETRICS 1996»
15 years 7 months ago
Integrating Performance Monitoring and Communication in Parallel Computers
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
Margaret Martonosi, David Ofelt, Mark Heinrich
IPPS
1999
IEEE
15 years 7 months ago
Mechanisms for Just-in-Time Allocation of Resources to Adaptive Parallel Programs
Adaptive parallel computations--computations that can adapt to changes in resource availability and requirement--can effectively use networked machines because they dynamically ex...
Arash Baratloo, Ayal Itzkovitz, Zvi M. Kedem, Yuan...
IPPS
2007
IEEE
15 years 9 months ago
Packet Reordering in Network Processors
Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workload...
S. Govind, R. Govindarajan, Joy Kuri
ASAP
1995
IEEE
145views Hardware» more  ASAP 1995»
15 years 6 months ago
An array processor for inner product computations using a Fermat number ALU
This paper explores an architecture for parallel independent computations of inner products over the direct product ring . The structure is based on the polynomial mapping of the ...
Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, Wil...