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» Performance pathologies in hardware transactional memory
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HPCA
2004
IEEE
16 years 16 hour ago
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
Using alternative cache indexing/hashing functions is a popular technique to reduce conflict misses by achieving a more uniform cache access distribution across the sets in the ca...
Mazen Kharbutli, Keith Irwin, Yan Solihin, Jaejin ...
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
15 years 6 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
FPL
2010
Springer
146views Hardware» more  FPL 2010»
14 years 9 months ago
Software Managed Distributed Memories in MPPAs
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
Robin Panda, Jimmy Xu, Scott Hauck
111
Voted
RTAS
2006
IEEE
15 years 5 months ago
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
Multiprocessor systems present serious challenges in the design of real-time systems due to the wider variation of execution time of an instruction sequence compared to a uniproce...
Jae W. Lee, Krste Asanovic
179
Voted
ASPLOS
2009
ACM
16 years 9 days ago
Maximum benefit from a minimal HTM
A minimal, bounded hardware transactional memory implementation significantly improves synchronization performance when used in an operating system kernel. We add HTM to Linux 2.4...
Owen S. Hofmann, Christopher J. Rossbach, Emmett W...