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71
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ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
15 years 6 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
OOPSLA
2004
Springer
15 years 3 months ago
Transparent proxies for java futures
A proxy object is a surrogate or placeholder that controls access to another target object. Proxies can be used to support distributed programming, lazy or parallel evaluation, ac...
Polyvios Pratikakis, Jaime Spacco, Michael W. Hick...
ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
15 years 6 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
76
Voted
EUROPAR
2007
Springer
15 years 3 months ago
Asynchronous Distributed Power Iteration with Gossip-Based Normalization
The dominant eigenvector of matrices defined by weighted links in overlay networks plays an important role in many peer-to-peer applications. Examples include trust management, im...
Márk Jelasity, Geoffrey Canright, Kenth Eng...
IMC
2005
ACM
15 years 3 months ago
Novel Approaches to End-to-End Packet Reordering Measurement
By providing the best-effort service, the Internet Protocol (IP) does not maintain the same order of packets sent out by a host. Therefore, due to the route change, parallelism in...
Xiapu Luo, Rocky K. C. Chang