42 search results - page 2 / 9 » Physical placement driven by sequential timing analysis |
84
Voted
EDBT
2004
ACM
15 years 9 months ago
2004
ACM
Due to the large difference between seek time and transfer time in current disk technology, it is advantageous to perform large I/O using a single sequential access rather than mu...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
62
Voted
VLSI
2007
Springer
15 years 3 months ago
2007
Springer
— While physically driven synthesis techniques have proven to be an effective method to meet tight timing constraints required by a design, the incremental placement step during ...
105
Voted
GLVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...