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TODAES
2008

69views more TODAES 2008»

Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming

14 years 11 months ago

Download www.ee.ucla.edu

Yu Hu, Yan Lin, Lei He, Tim Tuan

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DAC
2006
ACM

148views Computer Architecture» more DAC 2006»

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction

16 years 6 days ago

Download www.ee.ucla.edu

Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...

Yu Hu, Yan Lin, Lei He, Tim Tuan

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