351 search results - page 17 / 71 » Plug-and-Play Architectural Design and Verification |
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
101
click to vote
DAC
1996
ACM
15 years 1 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in ...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
Modern combinational equivalence checking (CEC) engines are complicated programs which are difficult to verify. In this paper we show how a modern CEC engine can be modified to pr...
69
Voted
DAC
2003
ACM
15 years 10 months ago
2003
ACM
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...