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DAC
2005
ACM
15 years 10 months ago
StressTest: an automatic approach to test generation via activity monitors
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
15 years 10 months ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...
CCS
2007
ACM
15 years 3 months ago
Analysis of three multilevel security architectures
Various system architectures have been proposed for high assurance enforcement of multilevel security. This paper provides an analysis of the relative merits of three architectura...
Timothy E. Levin, Cynthia E. Irvine, Clark Weissma...
DAC
2005
ACM
14 years 11 months ago
Matlab as a development environment for FPGA design
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algo...
Tejas M. Bhatt, Dennis McCain
DAC
1996
ACM
15 years 1 months ago
RTL Emulation: The Next Leap in System Verification
ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL ...
Sanjay Sawant, Paul Giordano