Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
Current design automation methodologies are becoming incapable of achieving design closure especially in the presence of deep submicron effects. This paper addresses the issue of ...
Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Cho...
This paper presents a method for prototyping grasp-sensitive surfaces using optical fibers. In this system one end of a fiber bundle is attached to an image sensor. The other en...
While pervasive technologies explore new gaming styles, traditional games, such as cards and tabletop games are still appealing and have various irreplaceable flavors. We point ou...