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» Post-Silicon Debug Using Programmable Logic Cores
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DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 3 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
72
Voted
POPL
2010
ACM
15 years 7 months ago
Generating Compiler Optimizations from Proofs
We present an automated technique for generating compiler optimizations from examples of concrete programs before and after improvements have been made to them. The key technical ...
Ross Tate, Michael Stepp, Sorin Lerner
78
Voted
FPGA
1995
ACM
118views FPGA» more  FPGA 1995»
15 years 1 months ago
An SBus Monitor Board
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask
ISTA
2008
14 years 11 months ago
A Framework for Building Mapping Operators Resolving Structural Heterogeneities
Seamless exchange of models among different modeling tools increasingly becomes a crucial prerequisite for the success of modeldriven engineering. Current best practices use model ...
Gerti Kappel, Horst Kargl, Thomas Reiter, Werner R...
ASPLOS
2011
ACM
14 years 1 months ago
Specifying and checking semantic atomicity for multithreaded programs
In practice, it is quite difficult to write correct multithreaded programs due to the potential for unintended and nondeterministic interference between parallel threads. A funda...
Jacob Burnim, George C. Necula, Koushik Sen