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IPPS
2007
IEEE
15 years 6 months ago
Improving MPI Independent Write Performance Using A Two-Stage Write-Behind Buffering Method
Many large-scale production applications often have very long executions times and require periodic data checkpoints in order to save the state of the computation for program rest...
Wei-keng Liao, Avery Ching, Kenin Coloma, Alok N. ...
101
Voted
CODES
2004
IEEE
15 years 4 months ago
CPU scheduling for statistically-assured real-time performance and improved energy efficiency
We present a CPU scheduling algorithm, called Energy-efficient Utility Accrual Algorithm (or EUA), for battery-powered, embedded real-time systems. We consider an embedded softwar...
Haisang Wu, Binoy Ravindran, E. Douglas Jensen, Pe...
IEEEPACT
2005
IEEE
15 years 6 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove
114
Voted
IPPS
2006
IEEE
15 years 6 months ago
A decomposition approach for optimizing the performance of MPI libraries
MPI provides a portable message passing interface for many parallel execution platforms but may lead to inefficiencies for some platforms and applications. In this article we sho...
O. Hartmann, Matthias Kühnemann, Thomas Raube...
105
Voted
CODES
2007
IEEE
15 years 6 months ago
Performance improvement of block based NAND flash translation layer
With growing capacities of flash memories, an efficient layer to manage read and write access to flash is required. NFTL is a widely used block based flash translation layer de...
Siddharth Choudhuri, Tony Givargis