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DATE
2005
IEEE
127views Hardware» more  DATE 2005»
15 years 7 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
BMCBI
2010
165views more  BMCBI 2010»
15 years 2 months ago
Filtering, FDR and power
Background: In high-dimensional data analysis such as differential gene expression analysis, people often use filtering methods like fold-change or variance filters in an attempt ...
Maarten van Iterson, Judith M. Boer, Renée ...
105
Voted
ICCAD
2001
IEEE
113views Hardware» more  ICCAD 2001»
15 years 10 months ago
The Design and Optimization of SOC Test Solutions
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
Erik Larsson, Zebo Peng, Gunnar Carlsson
ICCAD
2007
IEEE
135views Hardware» more  ICCAD 2007»
15 years 10 months ago
A selective pattern-compression scheme for power and test-data reduction
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
Chia-Yi Lin, Hung-Ming Chen
126
Voted
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
15 years 7 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...