462 search results - page 15 / 93 » Power Efficient Data Cache Designs |
132
Voted
CODES
2011
IEEE
14 years 8 days ago
2011
IEEE
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
110
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ISLPED
2010
ACM
15 years 20 days ago
2010
ACM
Runtime characteristics of individual threads (such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems...
104
Voted
ASPLOS
2008
ACM
15 years 2 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
108
Voted
HPCA
2008
IEEE
16 years 25 days ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
87
Voted
MICRO
2006
IEEE
15 years 6 months ago
2006
IEEE
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multi...