1238 search results - page 13 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
MICRO
2008
IEEE
15 years 5 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
DAC
2000
ACM
15 years 3 months ago
2000
ACM
DAC
2010
ACM
15 years 3 months ago
2010
ACM
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation ...
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ISPA
2007
Springer
15 years 5 months ago
2007
Springer
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...