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DAC
1996
ACM
15 years 3 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
89
Voted
EH
2005
IEEE
134views Hardware» more  EH 2005»
15 years 5 months ago
A Move Processor for Bio-Inspired Systems
The structure and operation of multi-cellular organisms relies, among other things, on the specialization of the cells’ physical structure to a finite set of specific operatio...
Gianluca Tempesti, Pierre-André Mudry, Ralp...
HPCA
2008
IEEE
15 years 12 months ago
Power-Efficient DRAM Speculation
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti,...
CASES
2006
ACM
15 years 3 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...
CSE
2009
IEEE
15 years 20 days ago
Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores
In this paper we present the design of a novel embedded processor architecture (which we call a
Amit Pande, Joseph Zambreno