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ICCD
2002
IEEE
114views Hardware» more  ICCD 2002»
15 years 8 months ago
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Che...
VLSI
2007
Springer
15 years 5 months ago
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor
Replacing functional units of an extensible processor with reconfigurable functional units enhances performance and flexibility of processors to execute custom instructions. That ...
Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Za...
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
15 years 6 months ago
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and de...
Vasileios Kontorinis, Amirali Shayan, Dean M. Tull...
CP
2008
Springer
15 years 1 months ago
A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine
The Cell BE processor provides both scalable computation power and flexibility, and it is already being adopted for many computational intensive applications like aerospace, defens...
Luca Benini, Michele Lombardi, Michela Milano, Mar...
MJ
2006
138views more  MJ 2006»
14 years 11 months ago
A CAM-based keyword match processor architecture
This paper demonstrates a keyword match processor capable of performing fast dictionary search with approximate match capability. Using a content addressable memory with processor...
Long Bu, John A. Chandy