Sciweavers

1238 search results - page 33 / 248
» Power Efficient Processor Architecture and The Cell Processo...
Sort
View
RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
15 years 4 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
LCPC
2005
Springer
15 years 5 months ago
Compiler Control Power Saving Scheme for Multi Core Processors
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten developmen...
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroak...
CODES
2011
IEEE
13 years 11 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
ICCD
2002
IEEE
228views Hardware» more  ICCD 2002»
15 years 8 months ago
JMA: The Java-Multithreading Architecture for Embedded Processors
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
Panit Watcharawitch, Simon W. Moore
SIGOPS
2008
104views more  SIGOPS 2008»
14 years 11 months ago
PipesFS: fast Linux I/O in the unix tradition
This paper presents PipesFS, an I/O architecture for Linux 2.6 that increases I/O throughput and adds support for heterogeneous parallel processors by (1) collapsing many I/O inte...
Willem de Bruijn, Herbert Bos