1238 search results - page 58 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
110
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RTCSA
2007
IEEE
15 years 6 months ago
2007
IEEE
Code optimization of the offset assignment generated in embedded systems allows for power and space efficient systems. We propose a new heuristic that uses edge classification to ...
115
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TCAD
2002
14 years 11 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
FPL
2005
Springer
15 years 5 months ago
2005
Springer
A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-onChip (MPSoC) architectures. In an earlier paper we proposed a energ...
126
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ERSA
2010
14 years 9 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...