173 search results - page 26 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
QSIC
2007
IEEE
15 years 4 months ago
2007
IEEE
The advanced electric power grid is a complex real-time system having both Cyber and Physical components. While each component may function correctly, independently, their composi...
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CODES
2006
IEEE
15 years 1 months ago
2006
IEEE
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
CASES
2006
ACM
15 years 3 months ago
2006
ACM
Dynamic voltage scaling and sleep state control have been shown to be extremely effective in reducing energy consumption in CMOS circuits. Though plenty of research papers have st...
DFT
2006
IEEE
15 years 1 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...