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» Power and performance optimization at the system level
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GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
16 years 12 days ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...
ICCAD
2003
IEEE
210views Hardware» more  ICCAD 2003»
16 years 2 months ago
Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems
Energy consumption is an important performance parameter for portable and wireless embedded systems. However, energy consumption must be carefully balanced with real-time responsi...
Vishnu Swaminathan, Krishnendu Chakrabarty
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
16 years 6 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
TMI
2002
78views more  TMI 2002»
15 years 5 months ago
A Quasi-Static Analysis for a Class of Induced-Current EIT Systems using Discrete Coils
A discrete coil EIT system is investigated for the general case of an eccentric circular inhomogeneity. The solution methodology of the forward problem of this system is explained....
Adnan Koksal, B. Murat Eyuboglu, Mehmet Demirbilek
HPDC
2012
IEEE
13 years 8 months ago
VNET/P: bridging the cloud and high performance computing through fast overlay networking
networking with a layer 2 abstraction provides a powerful model for virtualized wide-area distributed computing resources, including for high performance computing (HPC) on collec...
Lei Xia, Zheng Cui, John R. Lange, Yuan Tang, Pete...