Sciweavers

1850 search results - page 210 / 370
» Power and performance optimization at the system level
Sort
View
DATE
2004
IEEE
110views Hardware» more  DATE 2004»
15 years 10 months ago
Interactive Cosimulation with Partial Evaluation
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimizatio...
Patrick Schaumont, Ingrid Verbauwhede
196
Voted
IWCMC
2006
ACM
16 years 3 days ago
Optimal hierarchical energy efficient design for MANETs
Due to the growing interest in mobile wireless Ad-Hoc networks’ (MANETs) applications, researchers have proposed many routing protocols that differ in their objective. Energy ef...
Wasim El-Hajj, Dionysios Kountanis, Ala I. Al-Fuqa...
183
Voted
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
13 years 8 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
EMSOFT
2004
Springer
15 years 11 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
ICIP
2001
IEEE
16 years 7 months ago
Turbo coding for sample-level watermarking in the DCT domain
Coding at the sample level in still image watermarking takes advantage of avoiding a non-optimum initial diversity stage, used in many watermarking systems for tailoring Gaussian ...
Fabiano Baldo, Federico Pérez Gonzál...