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» Power and performance optimization at the system level
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ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
15 years 2 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...
FDL
2005
IEEE
15 years 3 months ago
SystemC-Based Communication and Performance Analysis
In today’s electronic system-level (ESL) design processes, an early analysis of a system’s communication and nce characteristics is becoming a key challenge. The availability ...
Axel G. Braun, Joachim Gerlach, Wolfgang Rosenstie...
VTC
2006
IEEE
15 years 3 months ago
Reduction of Amplitude Clipping Level with OFDM/TDM
—The OFDM signals have a problem of high peak-to-average power ratio (PAPR). Hence, a large transmit-power backoff or amplitude clipping is required. The amplitude clipping cause...
Haris Gacanin, Shinsuke Takaoka, Fumiyuki Adachi
ROBOTICA
2008
121views more  ROBOTICA 2008»
14 years 9 months ago
Kinematic and dynamic performance analysis of artificial legged systems
This paper studies the mechanical configuration and the periodic gaits of multi-legged locomotion systems based on its kinematic and dynamic models. The purpose is to determine the...
Manuel F. Silva, José António Tenrei...
CODES
2004
IEEE
15 years 1 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan