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» Power and performance optimization at the system level
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ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
15 years 1 months ago
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
Aurobindo Dasgupta, Ramesh Karri
LCN
2003
IEEE
15 years 3 months ago
Performance Analysis of IP Paging Protocol in IEEE 802.11 Networks
Recently, IEEE 802.11 wireless networks have been widely deployed in public areas for mobile Internet services. In the public wireless LAN systems, paging function is necessary to...
Sangheon Pack, Ved Kafle, Yanghee Choi
117
Voted
ABIALS
2008
Springer
15 years 4 months ago
A Two-Level Model of Anticipation-Based Motor Learning for Whole Body Motion
Abstract. We present a model of motor learning based on a combination of Operational Space Control and Optimal Control. Anticipatory processes are used both in the learning of the ...
Camille Salaün, Vincent Padois, Olivier Sigau...
GECCO
2004
Springer
136views Optimization» more  GECCO 2004»
15 years 3 months ago
System Level Hardware-Software Design Exploration with XCS
Abstract. The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip. An Embedded System has to satis...
Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciu...
ICC
2008
IEEE
133views Communications» more  ICC 2008»
15 years 4 months ago
Memoryless Relay Strategies for Two-Way Relay Channels: Performance Analysis and Optimization
— We consider relaying strategies for two-way relay channels, where two terminals transmits simultaneously to each other with the help of relays. A memoryless system is considere...
Tao Cui, Jörg Kliewer