157 search results - page 12 / 32 » Power and performance tradeoffs using various caching strate... |
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
Multi-core architectures introduce a new granularity at which process variations may occur, yielding asymmetry among cores that were designed—and that software expects—to be s...
ASPDAC
2005
ACM
14 years 12 months ago
2005
ACM
Ever scaling process technology makes embedded systems more vulnerable to soft errors than in the past. One of the generic methods used to fight soft errors is based on duplicati...
CISS
2011
IEEE
14 years 1 months ago
2011
IEEE
In this paper, we study both the jamming capability of the cognitiveradio-based jammers and the anti-jamming capability of the cognitive radio networks. We first setup the models...
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
76
Voted
IEEEPACT
2008
IEEE
15 years 4 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...